Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=/home/avn/work/ethond_fix/soc_files --output-directory=/home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis --file-set=QUARTUS_SYNTH --report-file=html:/home/avn/work/ethond_fix/soc_files/soc_ethond/soc_ethond.html --report-file=sopcinfo:/home/avn/work/ethond_fix/soc_files/soc_ethond.sopcinfo --report-file=cmp:/home/avn/work/ethond_fix/soc_files/soc_ethond/soc_ethond.cmp --report-file=qip:/home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/soc_ethond.qip --report-file=svd:/home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/soc_ethond.svd --report-file=regmap:/home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/soc_ethond.regmap --report-file=xml:/home/avn/work/ethond_fix/soc_files/soc_ethond/soc_ethond.xml --report-file=debuginfo:/home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/soc_ethond.debuginfo --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSEBA4U19C8 --system-info=DEVICE_SPEEDGRADE=8 --component-file=/home/avn/work/ethond_fix/soc_files/soc_ethond.qsys --language=VERILOG
Progress: Loading soc_files/soc_ethond.qsys
Progress: Reading input file
Progress: Adding hps_0 [altera_hps 14.0]
Progress: Parameterizing module hps_0
Progress: Adding clock_bridge_0 [altera_clock_bridge 14.0]
Progress: Parameterizing module clock_bridge_0
Progress: Adding tx_msgdma_0 [altera_msgdma 14.0]
Progress: Parameterizing module tx_msgdma_0
Progress: Adding tx_msgdma_1 [altera_msgdma 14.0]
Progress: Parameterizing module tx_msgdma_1
Progress: Adding rx_msgdma_0 [altera_msgdma 14.0]
Progress: Parameterizing module rx_msgdma_0
Progress: Adding rx_msgdma_1 [altera_msgdma 14.0]
Progress: Parameterizing module rx_msgdma_1
Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 14.0]
Progress: Parameterizing module mm_bridge_0
Progress: Adding reset_bridge_0 [altera_reset_bridge 14.0]
Progress: Parameterizing module reset_bridge_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: soc_ethond.hps_0: HLGPI is not available for Device 5CSEBA4U19C8 (484 pins)
Info: soc_ethond: Generating soc_ethond "soc_ethond" for QUARTUS_SYNTH
Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender
Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender
Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_001.sender
Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_001.sender
Info: hps_0: "Running  for module: hps_0"
Info: hps_0: HLGPI is not available for Device 5CSEBA4U19C8 (484 pins)
Info: hps_0: "soc_ethond" instantiated altera_hps "hps_0"
Info: tx_msgdma_0: "soc_ethond" instantiated altera_msgdma "tx_msgdma_0"
Info: rx_msgdma_0: "soc_ethond" instantiated altera_msgdma "rx_msgdma_0"
Info: mm_bridge_0: "soc_ethond" instantiated altera_avalon_mm_bridge "mm_bridge_0"
Info: mm_interconnect_0: "soc_ethond" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: mm_interconnect_1: "soc_ethond" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "soc_ethond" instantiated altera_irq_mapper "irq_mapper"
Info: irq_mapper_001: "soc_ethond" instantiated altera_irq_mapper "irq_mapper_001"
Info: rst_controller: "soc_ethond" instantiated altera_reset_controller "rst_controller"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: dispatcher_internal: "tx_msgdma_0" instantiated modular_sgdma_dispatcher "dispatcher_internal"
Info: read_mstr_internal: "tx_msgdma_0" instantiated dma_read_master "read_mstr_internal"
Info: write_mstr_internal: "rx_msgdma_0" instantiated dma_write_master "write_mstr_internal"
Info: tx_msgdma_0_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "tx_msgdma_0_csr_translator"
Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
Info: tx_msgdma_0_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "tx_msgdma_0_csr_agent"
Info: tx_msgdma_0_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "tx_msgdma_0_csr_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
Info: router_007: "mm_interconnect_0" instantiated altera_merlin_router "router_007"
Info: router_012: "mm_interconnect_0" instantiated altera_merlin_router "router_012"
Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_avalon_sc_fifo.v
Info: tx_msgdma_0_csr_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "tx_msgdma_0_csr_burst_adapter"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_arbitrator.sv
Info: tx_msgdma_0_csr_rsp_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "tx_msgdma_0_csr_rsp_width_adapter"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: rx_msgdma_1_mm_write_translator: "mm_interconnect_1" instantiated altera_merlin_master_translator "rx_msgdma_1_mm_write_translator"
Info: rx_msgdma_1_mm_write_agent: "mm_interconnect_1" instantiated altera_merlin_master_agent "rx_msgdma_1_mm_write_agent"
Info: hps_0_f2h_axi_slave_agent: "mm_interconnect_1" instantiated altera_merlin_axi_slave_ni "hps_0_f2h_axi_slave_agent"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_avalon_sc_fifo.v
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_address_alignment.sv
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_004: "mm_interconnect_1" instantiated altera_merlin_router "router_004"
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_002: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux_002"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /home/avn/work/ethond_fix/soc_files/soc_ethond/synthesis/submodules/altera_merlin_arbitrator.sv
Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: soc_ethond: Done "soc_ethond" with 42 modules, 108 files
Info: ip-generate succeeded.
Info: Finished: Create HDL design files for synthesis
